1. Field of the Invention
The present invention relates to a technique for detecting a disconnection of a semiconductor device.
2. Description of Related Art
A safety function for automatically avoiding a life-threatening condition is mounted in an automobile, a gas meter, and so on. Such a function is realized by a semiconductor device (hereinafter referred to as “microcomputer”) which is connected with diverse sensors. When an input signal line of such a microcomputer is disconnected, no significant signal is input from the sensors, and the microcomputer cannot detect the occurrence of an abnormal state. Then, there occurs a severe problem that the safety function is not executed when needed. With an aim to prevent the erroneous determination of the microcomputer described above, a demand is made on a technique for surely detecting the disconnection.
In a normal disconnection detecting method, for example, in the case of a microcomputer having an A/D conversion function, after the interior of the microcomputer has been initialized to 0 V, the microcomputer is connected to the input signal line. When a voltage value developed by A/D conversion of an input signal falls within a set value to be determined as a disconnection, it is determined that there occurs the disconnection. However, in the detecting method of this type, in the case where a wiring capacity outside of the microcomputer is very large as compared with a capacity of a sample and hold capacitor inside of the microcomputer, after the interior of the microcomputer has been initialized to 0 V, the microcomputer is connected to the input signal line. In this case, because the wiring capacity outside of the microcomputer charges the capacity of the sample and hold capacitor, the voltage value developed by the A/D conversion potentially reaches a voltage value that is not determined as a disconnection although the disconnection occurs.
FIG. 6 shows the configuration of a semiconductor device according to a related art described in Patent Document 1 (Japanese Patent No. 3861874). In the figure, references VIN1 and VIN2 indicate inputs of sensors which are substituted with voltage sources. Those VIN1 and VIN2 are connected to terminals AIN1 and AIN2, respectively. An A/D converter 101 includes an input Ch selection switch section 102, a comparator 103, an A/D conversion control section 104, a comparative voltage selection section 105, a conversion register section 106, an S/N (sample and hold) capacitor initialization SW (switch) 107, a parity operation section 108, and a register storage section 109 having Ch registers 00 to 11. The A/D converter 101 is connected to a control section 110 through signal lines of an address bus, a data bus, an RD (read request), and a WR (write request), which operate on the basis of clock signals φ. The control section 110 is formed as a normal computer, and made up of a CPU (central processing unit), a ROM (road only memory), an RAM (random access memory), an input/output circuit, bus lines connecting those configurations, etc., which are well known and not shown). The CPU executes control according to a program and data which are stored in the ROM and the RAM. Data read from the A/D converter 101 and the abnormality determination of the A/D converter 101 are executed by the program included in the control section 110.
Subsequently, a description will be given of the operation of the semiconductor device configured as described above. The A/D converter 101 operates on the basis of a CLK signal supplied from the control section 110. In an example of FIG. 6, a voltage across an S/H capacitor C1 becomes a lower reference voltage VREF− (0 V). When the initialization of the S/H capacitor C1 has been completed, the S/H capacitor initialization SW 107 and an SW3 are opened to select an AIN2 (Ch10). When the AIN2 (Ch10) has been selected, an SW10, an SW1, and the SW3 are closed, and electric charge corresponding to a value of the VIN2 is stored in the S/H capacitor C1. When the electric charge has been stored, the SW1 and the SW3 are opened, and the SW2 is closed to execute A/D conversion. A comparative voltage generated on the basis of an upper reference voltage VREF+ and the lower reference voltage VREF− are compared with a voltage of the electric charge stored in the S/H capacitor C1 by the comparative voltage selection section 105, and the comparison result is sequentially held in the conversion register section 106. Then, at a point of time when the VIN2 coincides with the comparative voltage, a value held in the conversion register section 106 is stored as an A/D conversion value in a Ch register 10 in the register storage section 109 (a conversion result storage section in a known technique). Thereafter, the SW1 and the SW2 are opened. Those processing is controlled by the A/D conversion control section 104.
Thereafter, the S/H capacitor initialization SW 107 and the SW3 are again closed to initialize the S/H capacitor C1. When the initialization of the S/H capacitor C1 has been completed, an S/H capacitor initialization SW25 and the SW3 are opened, and a subsequent Ch is selected to implement the A/D conversion of the subsequent Ch.
Subsequently, a description will be given of a method of detecting abnormality in the semiconductor device. When A/D conversion has been executed, the electric charge that has been stored in the S/H capacitor C1 becomes electric charge when the electric charge when the S/H capacitor has been initialized, that is, a result obtained by subjecting VREF− (0 V) to A/D conversion. As usual, when an important sensor input is subjected to A/D conversion, an effective value of the input voltage (VIN1, VIN2) from the sensors is a value ranging from 10 to 90% of a reference voltage, and other values are set as abnormal values at the time of disconnection (including short-circuiting). When the reference voltage is set to 5 V (the upper reference voltage VREF+ is 5 V, the lower reference voltage is 0 V), the effective value of the input voltage from the sensors is 0.5 to 4.5 V, and other values (that is, a value smaller than 0.5 V, or a value larger than 4.5 V) are allowed to determine that the sensor is abnormal. When the input from each selected Ch is a normal value (for example, 3 V), electric charge corresponding to 3 V is stored in the S/H capacitor C1 to execute A/D conversion, and an A/D conversion result of 3 V is obtained. However, when the S/H capacitor C1 is abnormal, or when disconnection abnormality exists in an input system from the sensors, because no electric charge is stored in the S/H capacitor C1, the electric charge stored in the S/H capacitor C1 remains in a state where the S/H capacitor C1 has been initialized (zero). At that time, when A/D conversion is executed, the conversion result of 0 V is obtained, and the control section 110 can determine that the A/D converter 101 is abnormal.
Further, one (for example, the input terminal VIN1) of the inputs from the A/D converter 101 may be an arbitrary voltage (for example, 2.5 V) generated by a stabilized power supply different from a stabilized power supply that is connected to an A/D supply voltage (for example, 5 V) applied to the A/D converter 101, or the reference voltage (VREF+, VREF−). In this case, the control section 110 compares a real conversion result of that voltage with an estimated value of the conversion result that has been stored in the storage section of the control section 110 in advance. When a difference therebetween is equal to or higher than a given value, it is determined that the difference is abnormal. As a result, like the above case, the abnormality of the A/D supply voltage, the comparative voltage selection section 105, and the input terminal VIN1 can be detected.